2014/01/19 leewk2547 26 페이지 2,000원 다운 0회 구매평가 

library ieee; use ieee.std_logic_1164.all; entity logic1 is port(a,b,c :in bit; y :out bit); end logic1; architecture sample of logic1 is signal w, x : bit; begin no1: process(a,b) begin if (a=1)...

2014/01/19 leewk2547 26 페이지 2,000원 다운 0회 구매평가 

library ieee; use ieee.std_logic_1164.all; entity andgate is port( sw1 : in std_logic; sw2 : in std_logic; led : out std_logic); end andgate; architecture sample of andgate is begin led <= sw1 and...